The present invention relates to memory technology, and more particularly to memories used in processor-based systems.
Many current processors include one or more memories integrated into the processor. Such memories include cache structures, which are typically formed of static random access memory (SRAM), as well as read only memories (ROMs) such as microcode. Microcode is a way of using programmability of microarchitectural components to enhance functionality, and to apply updates to an existing design (e.g., a processor design). In such manner, die area, power consumption and design cost may be kept under control.
Recent trends have migrated more advanced functionality to microcode of a processor core. Many processor designs include thousands of lines of microcode, and microcode storage can consume up to 20% of the die area of a processor. Microcode bloat increases costs in terms of die area and associated power consumption. The cost for microcode storage is especially acute where small footprint dies and reduced power consumption are required, such as in processors used in embedded applications.
A need thus exists to provide for microcode storage with reduced size and power consumption.